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lnk603-606/613-616 linkswitch-ii family www.powerint.com june 2008 energy-effi cient, accurate cv/cc switcher for adapters and chargers ? output power table product 3 85-265 vac adapter 1 open frame 2 lnk603/613pg/dg 2.5 w 3.3 w lnk604/614pg/dg 3.5 w 4.1 w lnk605/615pg/dg 4.5 w 5.1 w lnk606/616pg/gg 5.5 w 6.1 w table 1. output power table. notes: 1. minimum continuous power in a typical non-ventilated enclosed adapter measured at +50 c ambient, device, t j <100 c. 2. maximum practical continuous power in an open frame design with adequate heatsinking, measured at 50 c ambient (see key applications considerations section for more information). 3. packages: p: dip-8c, g: smd-8c, d: so-8c. product highlights dramatically simpli? es cv/cc converters eliminates optocoupler and all secondary cv/cc control circuitry eliminates all control loop compensation circuitry advanced performance features compensates for transformer inductance tolerances compensates for input line voltage variations compensates for cable voltage drop (lnk61x series) compensates for external component temperature variations very tight ic parameter tolerances using proprietary trimming technology frequency jittering greatly reduces emi ? lter cost even tighter output tolerances achievable with external resistor selection/trimming advanced protection/safety features auto-restart protection reduces power delivered by >95% for output short circuit and control loop faults (open and shorted components) hysteretic thermal shutdown C automatic recovery reduces power supply returns from the ? eld meets hv creepage requirements between drain and all other pins both on the pcb and at the package ecosmart ? C energy ef? cient easily meets all global energy ef? ciency regulations no-load consumption <200 mw at 230 vac and down to below 30 mw with optional external bias on/off control provides constant ef? ciency down to very light loads C ideal for cec and energy star 2.0 regulations no current sense resistors C maximizes ef? ciency green package halogen free and rohs compliant package applications chargers for cell/cordless phones, pdas, mp3/portable audio devices, adapters, led drivers, etc. description the linkswitch-ii dramatically simpli? es low power cv/cc charger designs by eliminating an optocoupler and secondary control circuitry. the device introduces a revolutionary control technique to provide very tight output voltage and current regulation, compensating for transformer and internal parameter tolerances along with input voltage variations. the device incorporates a 700 v power mosfet, a novel on/off control state machine, a high voltage switched current source for self biasing, frequency jittering, cycle-by-cycle current limit and hysteretic thermal shutdown circuitry onto a monolithic ic. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 1. typical application/performance C not a simpli? ed circuit (a) and output characteristic envelope (b). (see application section for more information). linkswitch-ii wide range hv dc input pi-4960-060608 d s fb bp/m i o v o 5% 10% pi-4906-041008 (a) typical application schematic (b) output characteristic
rev. c 06/08 2 lnk603-606/613-616 www.powerint.com pin functional description drain (d) pin: this pin is the power mosfet drain connection. it provides internal operating current for both start-up and steady-state operation. bypass/multi-functional programmable (bp/m) pin: this pin has multiple functions: it is the connection point for an external bypass capacitor for the internally generated 6 v supply. it is a mode selection for the cable drop compensation for lnk61x series. feedback (fb) pin: during normal operation, switching of the power mosfet is controlled by this pin. this pin senses the ac voltage on the bias winding. this control input regulates both the output voltage in cv mode and output current in cc mode based on the ? yback voltage of the bias winding. the internal inductance correction circuit uses the forward voltage on the bias winding to sense the bulk capacitor voltage. source (s) pin: this pin is internally connected to the output mosfet source for high voltage power and control circuit common returns. 1. 2. figure 2 functional block diagram. figure 3. pin con? guration. pi-4 9 08-041508 source (s) leading edge blanking + - + - + - drain (d) regulator 6 v bypass (bp/m) feedback (fb) source (s) fb out reset 6 v 5 v t sample-out t sample-input v ilimit i lim v ilimit v th t sample-out t sample-input v ilimit 6.5 v drive i lim dc max dc max fb current limit comparator state machine cable drop compensation sample delay thermal shutdown oscillator fault auto-restart open-loop inductance correction constant current dq pi-34 9 1-012808 3a 3b d s bp/m s s fb p package (dip-8c) g package (smd-8c) d package (so-8c) 8 5 7 1 4 2 s 6 d s bp/m s s fb 8 5 7 1 4 2 s 6
rev. c 06/08 3 lnk603-606/613-616 www.powerint.com linkswitch-ii functional description the linkswitch-ii combines a high voltage power mosfet switch with a power supply controller in one device. similar to the linkswitch-lp and tinyswitch-iii it uses on/off control to regulate the output voltage. in addition, the switching frequency is modulated to regulate the output current to provide a constant current characteristic. the linkswitch-ii controller consists of an oscillator, feedback (sense and logic) circuit, 6 v regulator, over-temperature protection, frequency jittering, current limit circuit, leading-edge blanking, inductance correction circuitry, frequency control for constant current regulation and on/off state machine for cv control. inductance correction circuitry if the primary magnetizing inductance is either too high or low the converter will automatically compensate for this by adjusting the oscillator frequency. since this controller is designed to operate in discontinuous-conduction mode the output power is directly proportional to the set primary inductance and its tolerance can be completely compensated with adjustments to the switching frequency. constant current (cc) operation as the output voltage and therefore the ? yback voltage across the bias winding increases, the feedback pin voltage increases. the switching frequency is adjusted as the feedback pin voltage increases to provide a constant output current regulation. the constant current circuit and the inductance correction circuit are designed to operate concurrently in the cc region. constant voltage (cv) operation as the feedback pin approaches v fbth from the constant current regulation mode, the power supply transitions into cv operation. the switching frequency at this point is at its maximum value, corresponding to the peak power point of the cccv characteristic. the controller regulates the feedback pin voltage to remain at v fbth using an on/off state-machine. the feedback pin voltage is sampled 2.5 s after the turn-off of the high voltage switch. at light loads the current limit is also reduced to decrease the transformer ? ux density. output cable compensation this compensation provides a constant output voltage at the end of the cable over the entire load range in cv mode. as the converter load increases from no-load to the peak power point (transition point between cv and cc) the voltage drop introduced across the output cable is compensated by increasing the feedback pin reference voltage. the controller determines the output load and therefore the correct degree of compensation based on the output of the state machine. cable drop compensation for a 24 awg (0.3 ) cable is selected with c bp = 1 f and for a 26 awg (0.49 ) cable with c pb = 10 f. auto-restart and open-loop protection in the event of a fault condition such as an output short or an open loop condition the linkswitch-ii enters into an appropriate protection mode as described below. in the event the feedback pin voltage during the ? yback period falls below 0.7 v before the feedback pin sampling delay (~2.5 s) for a duration in excess of ~450 ms (auto-restart on- time (t ar-on ) the converter enters into auto-restart, wherein the power mosfet is disabled for 4 seconds (~8% auto-restart duty cycle). the auto-restart alternately enables and disables the switching of the power mosfet until the fault condition is removed. in addition to the conditions for auto-restart described above, if the sensed feedback pin current during the forward period of the conduction cycle (switch on time) falls below 120 a, the converter annunciates this as an open-loop condition (top resistor in potential divider is open or missing) and reduces the auto-restart time from 450 msec to approximately 6 clock cycles (90 s), whilst keeping the disable period of 4 seconds. this effectively reduces the auto-restart duty cycle to less than 0.01%. over-temperature protection the thermal shutdown circuitry senses the die temperature. the threshold is set at 142 c typical with a 60 c hysteresis. when the die temperature rises above this threshold (142 c) the power mosfet is disabled and remains disabled until the die temperature falls by 60 c, at which point the mosfet is re-enabled. current limit the current limit circuit senses the current in the power mosfet. when this current exceeds the internal threshold (i limit ), the power mosfet is turned off for the remainder of that cycle. the leading edge blanking circuit inhibits the current limit comparator for a short time (t leb ) after the power mosfet is turned on. this leading edge blanking time has been set so that current spikes caused by capacitance and recti? er reverse recovery time will not cause premature termination of the mosfet conduction. the linkswitch-ii also contains a di/dt correction feature to minimize cc variation across the input line range. 6.0 v regulator the 6 v regulator charges the bypass capacitor connected to the bypass pin to 6 v by drawing a current from the voltage on the drain, whenever the mosfet is off. the bypass pin is the internal supply voltage node. when the mosfet is on, the device runs off of the energy stored in the bypass capacitor. extremely low power consumption of the internal circuitry allows the linkswitch-ii to operate continuously from the current drawn from the drain pin. a bypass capacitor value of either 1 f or 10 f is suf? cient for both high frequency decoupling and energy storage.
rev. c 06/08 4 lnk603-606/613-616 www.powerint.com applications example circuit description this circuit shown in figure 4 is con? gured as a primary-side regulated ? yback power supply utilizing the lnk613dg. with an average ef? ciency of 74% and <40 mw no-load input power this design easily exceeds the most stringent current energy ef? ciency requirements. input filter ac input power is recti? ed by diodes d1 through d4. the recti? ed dc is ? ltered by the bulk storage capacitors c1 and c2. inductor l1, c1 and c2 form a pi () ? lter, which attenuates conducted differential-mode emi noise. this con? guration along with power integrations transformer e-shield ? technology allow this design to meet emi standard en55022 class b with good margin without requiring a y capacitor, even with the output connected to safety earth ground. fusible resistor rf1 provides protection against catastrophic failure. this should be suitably rated (typically a wire wound type) to withstand the instantaneous dissipation while the input capacitors charge when ? rst connected to the ac line. lnk 613 primary the lnk613dg device (u1) incorporates the power switching device, oscillator, cc/cv control engine, startup, and protection functions. the integrated 700 v mosfet provides a large drain voltage margin in universal input ac applications, increasing reliability and also reducing the output diode voltage stress by allowing a greater transformer turns ratio. the device is completely self-powered from the bypass pin and decoupling capacitor c4. for the lnk61x devices, the bypass capacitor value also selects the amount of output cable voltage drop compensation. a 1 f value selects the standard compensation. a 10 f value selects the enhanced compensation. table 2 shows the amount of compensation for each device and bypass capacitor value. the lnk60x devices do not provide cable drop compensation. the optional bias supply formed by d6 and c5 provides the operating current for u1 via resistor r4. this reduces the no- load consumption from ~200 mw to <40 mw and also increases light load ef? ciency. the recti? ed and ? ltered input voltage is applied to one side of the primary winding of t1. the other side of the transformers primary winding is driven by the integrated mosfet in u1. the leakage inductance drain voltage spike is limited by an rcd-r clamp consisting of d5, r2, r3, and c3. output recti? cation the secondary of the transformer is recti? ed by d7, a 1 a, 40 v schottky barrier type for higher ef? ciency, and ? ltered by c7. if lower ef? ciency is acceptable then this can be replaced with a 1 a pn junction diode for lower cost. in this application c7 was sized to meet the required output voltage ripple speci? cation without requiring a post lc ? lter. to meet battery self discharge requirement the pre-load resistor has been replaced with a series resistor and zener network (r8 and vr1). however in designs where this is not a requirement a standard 1 k resistor can be used. output regulation the lnk613 regulates the output using on/off control in the constant voltage (cv) regulation region of the output character- figure 4. energy ef? cient usb charger power supply (74% average ef? ciency, <40 mw no-load input power). pi-5111-050808 d s fb bp r2 470 k 7 r3 300 7 r5 13 k 7 1% r7 200 7 r8 200 7 r6 8.87 k 7 1% r4 6.2 k 7 rf1 8.2 7 2 w d5 1n4007 d7 ss14 d6 ll4148 vr1 2mm5230b-7 4.7 v d1 1n4007 d2 1n4007 d3 1n4007 d4 1n4007 t1 ee16 510 8 1 2 4 nc 3 c7 680 m f 10 v c6 1 nf 100 v c1 4.7 m f 400 v c2 4.7 m f 400 v c4 1 m f 25 v c5 10 m f 16 v l1 1.5 mh c3 820 pf 1 kv dc output 5 v, 555 m a u1 lnk613dg linkswitch-ii ac input
rev. c 06/08 5 lnk603-606/613-616 www.powerint.com istic and frequency control for constant current (cc) regulation. the feedback resistors (r5 and r6) were selected using standard 1% resistor values to center both the nominal output voltage and constant current regulation thresholds. key application considerations output power table the data sheet maximum output power table (table 1) repre- sents the maximum practical continuous output power level that can be obtained under the following assumed conditions: the minimum dc input voltage is 90 v or higher at 85 vac input. the value of the input capacitance should be large enough to meet these criteria for ac input designs. secondary output of 5 v with a schottky recti? er diode. assumed ef? ciency of 70%. discontinuous mode operation (k p >1.3). the part is board mounted with source pins soldered to a suf? cient area of copper to keep the source pin tempera- ture at or below 90 c. ambient temperature of 50 c for open frame designs and an internal enclosure temperature of 60 c for adapter designs. note: higher output power are achievable if an output cc tolerance >10% is acceptable, allowing the device to be operated at a higher source pin temperature. output tolerance linkswitch-ii provides an overall output tolerance (including line, component variation and temperature) of 5% for the output voltage in cv operation and 10% for the output current during cc operation over a junction temperature range of 0 c to 100 c for the p/g package. for the d package (so8) additional cc variance may occur due to stress caused by the manufacturing ? ow (i.e. solder-wave immersion or ir re? ow). a sample power supply build is recommended to verify production tolerances for each design. bypass pin capacitor selection for linkswitch-ii 60x family of devices (without output cable voltage drop compensation) a 1 f bypass pin capacitor is recommended. the capacitor voltage rating should be greater than 7 v. the capacitors dielectric material is not important but tolerance of capacitor should be 50%. the capacitor must be physically located close to the linkswitch-ii bypass pin. for linkswitch-ii 61x family of devices (with output cable voltage drop compensation) the amount of output cable compensation can be selected with the value of the bypass pin capacitor. a value of 1 f selects the standard cable compensation. a 10 f capacitor selects the enhanced cable compensation. table 2 shows the amount of compensation for each linkswitch-ii device and capacitor value. the capacitor can be either ceramic or electrolytic but tolerance and temperature variation should be 50%. 1. 2. 3. 4. 5. 6. the output voltage that is entered into pixls design spreadsheet is the voltage at the end of the output cable when the power supply is delivering maximum power. the output voltage at the terminals of the supply is the value measured at the end of the cable multiplied by the output voltage change factor. linkswitch-ii layout considerations circuit board layout linkswitch-ii is a highly integrated power supply solution that integrates on a single die, both, the controller and the high voltage mosfet. the presence of high switching currents and voltages together with analog signals makes it especially important to follow good pcb design practice to ensure stable and trouble free operation of the power supply. see figure 5 for a recommended circuit board layout for linkswitch-ii. when designing a printed circuit board for the linkswitch-ii based power supply, it is important to follow the following guidelines: single point grounding use a single point (kelvin) connection at the negative terminal of the input ? lter capacitor for the linkswitch-ii source pin and bias winding return. this improves surge capabilities by returning surge currents from the bias winding directly to the input ? lter capacitor. bypass capacitor the bypass pin capacitor should be located as close as possible to the source and bypass pins. feedback resistors place the feedback resistors directly at the feedback pin of the linkswitch-ii device. this minimizes noise coupling. thermal considerations the copper area connected to the source pins provides the linkswitch-ii heat sink. a good estimate is that the linkswitch-ii will dissipate 10% of the output power. provide enough copper area to keep the source pin temperature below 90 c. higher temperatures are allowable only if an output current (cc) tolerance above 10% is acceptable. in this case a maximum source pin temperature below 110 c is recommended to provide margin for part to part r ds(on) variation. linkswitch-ii output cable voltage drop compensation device bypass pin capacitor value output voltage change factor lnk613 1 f 1.035 10 f 1.055 lnk614 1 f 1.045 10 f 1.065 lnk615 1 f 1.050 10 f 1.070 lnk616 1 f 1.060 10 f 1.090 table 2. cable compensation change factor vs device and bypass pin capacitor value.
rev. c 06/08 6 lnk603-606/613-616 www.powerint.com secondary loop area to minimize leakage inductance and emi the area of the loop connecting the secondary winding, the output diode and the output ? lter capacitor should be minimized. in addition, suf? cient copper area should be provided at the anode and cathode terminal of the diode for heatsinking. a larger area is preferred at the quiet cathode terminal. a large anode area can increase high frequency radiated emi. electrostatic discharge spark gap an trace is placed along the isolation barrier to form one electrode of a spark gap. the other electrode on the secondary is formed by the output return node. the spark gap directs esd energy from the secondary back to the ac input. the trace from the ac input to the spark gap electrode should be spaced away from other traces to prevent unwanted arcing occurring and possible circuit damage. drain clamp optimization linkswitch-ii senses the feedback winding on the primary side to regulate the output. the voltage that appears on the feed- back winding is a re? ection of the secondary winding voltage while the internal mosfet is off. therefore any leakage inductance induced ringing can affect output regulation. optimizing the drain clamp to minimize the high frequency ringing will give the best regulation. figure 6 shows the desired drain voltage waveform compared to figure 7 with a large undershoot due to the leakage inductance induced ring. this will reduce the output voltage regulation performance. to figure 5. pcb layout example showing 5.1 w design using p package. reduce this adjust the value of the resistor in series with the clamp diode. addition of a bias circuit for higher light load ef? ciency and lower no load input power consumption. the addition of a bias circuit can decrease the no load input power from ~200 mw down to less than 30 mw at 230 vac input. light load ef? ciency also increases which may avoid the need to use a schottky barrier vs pn junction output diode while still meeting average ef? ciency requirements. the power supply schematic shown in figure 4 has the bias circuit incorporated. diode d6, c5 and r4 form the bias circuit. as the output voltage is less than 8 v, an additional transformer winding is needed, ac stacked on top of the feedback winding. this provides a high enough voltage to supply the bypass pin even during low switching frequency operation at no-load. in figure 4 the additional bias winding (from pin 2 to pin 1) is stacked on top of the feedback winding (pin 4 to pin 2). diode d6 recti? es the output and c5 is the ? lter capacitor. a 10 uf capacitor is recommended to hold up the bias voltage at low switching frequencies. the capacitor type is not critical but the voltage rating should be above the maximum value of v bias . the recommended current into the bp pin is equal to ic supply current (~0.5 ma). the value of r4 is calculated according to (v bias C v bp )/i s2 , where v bias (10 v typ.) is the voltage across c5, i s2 (0.5 ma typ.) is the ic supply current and v bp (6.2 v typ.) is dc output pi-5110-050508 r5 c4 c5 c3 r4 d5 d3 r3 r1 c2 r1 c1 r6 r2 l2 d4 d2 d1 u1 d3 rf1 d7 t1 r8 c6 c7 c8 r9 output filter capacitors input stage primary clamp output diode snubber preload resistor spark gap bypass capacitor feedback resistors bypass supply components ac input ssss bp d fb linkswitch-ii
rev. c 06/08 7 lnk603-606/613-616 www.powerint.com pi-5093-041408 an overshoot is acceptable pi-5094-042408 negative ring may increase output ripple and/or degrade output regulation figure 6. desired drain voltage waveform with minimal leakage ringing undershoot. figure 7. undesirable drain voltage waveform with large leakage ring undershoot. the bp pin voltage. the parameters i s2 and v bp are provided in the parameter table of the linkswitch-ii data sheet. diode d6 can be any low cost diode such as fr102, 1n4148 or bav19/20/21. quick design checklist as with any power supply design, all linkswitch-ii designs should be veri? ed on the bench to make sure that component speci? cations are not exceeded under worst-case conditions. the following minimum set of tests is strongly recommended: maximum drain voltage C verify that peak v ds does not exceed 680 v at the highest input voltage and maximum output power. maximum drain current C at maximum ambient temperature, maximum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of trans- 1. 2. pi-5116-050808 d s fb bp r2 470 k 7 1 k 7 r3 300 7 r5 13 k 7 1% r6 9.31 k 7 1% d5 1n4007 d7 sl13 ti ee13 510 8 2 4 nc 3 c7 470 m f 10 v c1 4.7 m f 400 v c2 4.7 m f 400 v c4 1 m f 50 v l1 1 mh c3 820 pf 1 kv ac input dc outpu t u1 lnk613dg linkswitch-ii rf1 8.2 7 2 w d1 1n4007 d2 1n4007 d3 1n4007 d4 1n4007 former saturation and excessive leading edge current spikes. linkswitch-ii has a leading edge blanking time of 170 ns to prevent premature termination of the on-cycle. thermal check C at maximum output power, both minimum and maximum input voltage and maximum ambient tempera- ture; verify that temperature speci? cations are not exceeded for linkswitch-ii, transformer, output diodes and output capacitors. enough thermal margin should be allowed for part-to-part variation of the r ds(on) of linkswitch-ii, as speci? ed in the data sheet. to assure 10% cc tolerance a maximum source pin temperature of 90 oc is recommended. design tools up-to-date information on design tools can be found at the power integrations web site: www.powerint.com 3. figure 8. linkswitch-ii flyback power supply without bias supply.
rev. c 06/08 8 lnk603-606/613-616 www.powerint.com parameter symbol conditions source = 0 v; t j = 0 to 100 c (unless otherwise speci? ed) min typ max units control functions output frequency f osc t j = 25 c, v fb = v fbth t on i fb = 2 ma- s lnk603/6 59 66 73 khz lnk613/6 58 65 72 frequency ratio (constant current) f ratio(cc) t j = 25 c between v fb = 1.0 v and v fb = 1.6 v 1.59 1.635 1.68 frequency ratio (inductance correction) f ratio(ic) between t on i fb = 1.6 ma s and t on i fb = 2 ma s 1.160 1.215 1.265 frequency jitter peak-peak jitter compared to average frequency, t j = 25 c 7 % ratio of output frequency at auto-rst f osc(ar) t j = 25 c relative to f osc 12 16.5 21 % maximum duty cycle dc max (note 4,5) 55 % feedback pin voltage v fbth t j = 25 c see figure 19, c bp = 10 f lnk603/604p 1.815 1.840 1.865 v lnk603/604d 1.855 1.880 1.905 lnk605p, lnk605d 1.835 1.860 1.885 lnk606p, lnk606g 1.775 1.800 1.825 lnk613/614p 1.935 1.960 1.985 lnk613/614/615d 1.975 2.000 2.025 lnk615p 1.975 2.000 2.025 lnk616g, lnk616p 1.935 1.960 1.985 feedback pin voltage temperature coef? cient tc vfb -0.01 %/c feedback pin voltage at turn-off threshold v fb(ar) 0.65 0.72 0.79 v cable compensation factor fb lnk613 see figure 19 c bp = 1 f 1.035 c bp = 10 f 1.055 lnk614 see figure 19 c bp = 1 f 1.045 c bp = 10 f 1.065 absolute maximum ratings (1,4) drain voltage .................................. ......... ..............-0.3 v to 700 v drain peak current: lnk603/613 ............................. 320 ma lnk604/614 ............................. 400 ma lnk605/615 ............................. 504 ma lnk606/616 ............................. 656 ma peak negative pulsed drain current ................... ......... -100 ma (2) feedback voltage ................................................. ....... -0.3 v to 9 v feedback current ................................................. ............. 100 ma bypass pin voltage ..................................... ............. -0.3 v to 9 v storage temperature ...................................... .... -65 c to 150 c operating junction temperature.........................-40 c to 150 c lead temperature (3) .................................................................260 c notes: 1. all voltages referenced to source, t a = 25 c. 2. duration not to exceed 2 msec. 3. 1/16 in. from case for 5 seconds. 4. maximum ratings speci? ed may be applied, one at a time without causing permanent damage to the product. exposure to absolute maximum ratings for extended periods of time may affect product reliability. thermal impedance thermal impedance: p or g package: ( ja ) .......................... .........70 c/w (2) ; 60 c/w (3) ( jc ) (1) ............................................... ......... 11 c/w d package: ( ja .....................................100 c/w (2) ; 80 c/w (3) ( jc ) (1) .......................... ...........................30 c/w notes: 1. measured on pin 8 (source) close to plastic interface. 2. soldered to 0.36 sq. in. (232 mm 2 ), 2 oz. (610 g/m 2 ) copper clad. 3. soldered to 1 sq. in. (645 mm 2 ), 2 oz. (610 g/m 2 ) copper clad.
rev. c 06/08 9 lnk603-606/613-616 www.powerint.com parameter symbol conditions source = 0 v; t j = 0 to 100 c (unless otherwise speci? ed) min typ max units control functions (cont.) cable compensation factor fb lnk615 see figure 19 c bp = 1 f 1.05 c bp = 10 f 1.07 lnk616 see figure 19 c bp = 1 f 1.06 c bp = 10 f 1.09 switch on-time t on f osc = 66 khz v fb = v fbth (note 5) i fb = -500 a 4 s i fb = -1 ma 2 i fb = -1.5 ma 1.33 i fb = -2 ma 1 minimum switch on-time t on(min) (note 5) 700 ns feedback pin sampling delay t fb see figure 19 2.35 2.55 2.75 s drain supply current i s1 fb voltage > v fbth 280 330 a i s2 fb voltage = v fbth -0.1, switch on-time = t on (mosfet switching at f osc ) lnk6x3/4 440 520 lnk6x5 480 560 lnk6x6 520 600 bypass pin charge current i ch1 v bp = 0 v lnk6x3/4 -5.0 -3.4 -1.8 ma lnk6x5/6 -7.0 -4.8 -2.5 i ch2 v bp = 4 v lnk6x3/4 -4.0 -2.3 -1.0 lnk6x5/6 -5.6 -3.2 -1.4 bypass pin voltage v bp 5.65 6.00 6.25 v bypass pin voltage hysteresis v bph 0.70 1.00 1.20 v bypass pin shunt voltage v shunt 6.2 6.5 6.8 v circuit protection current limit i limit lnk6x3 di/dt = 50 ma/ s , t j = 25 c 186 200 214 ma lnk6x4 di/dt = 60 ma/ s , t j = 25 c 233 250 267 lnk6x5 di/dt = 70 ma/ s , t j = 25 c 293 315 337 lnk6x6 di/dt = 100 ma/ s , t j = 25 c 382 410 438 normalized output current i o t j = 25 c see figure 21 0.975 1.000 1.025 leading edge blanking time t leb t j = 25 c (see note 5) 170 215 ns thermal shutdown temperature t sd 135 142 150 c thermal shutdown hysteresis t sdh 60 c
rev. c 06/08 10 lnk603-606/613-616 www.powerint.com parameter symbol conditions source = 0 v; t j = 0 to 100 c (unless otherwise speci? ed) min typ max units output on-state resistance r ds(on) lnk6x3 i d = 50 ma t j = 25 c 24 28 t j = 100 c 36 42 lnk6x4 i d = 50 ma t j = 25 c 24 28 t j = 100 c 36 42 lnk6x5 i d = 62 ma t j = 25 c 16 19 t j = 100 c 24 28 lnk6x6 i d = 82 ma t j = 25 c 9.6 11 t j = 100 c 14 17 off-state leakage i dss1 v ds = 560 v see figure 20 t j = 125 c see note 3 50 a i dss2 v ds = 375 v see figure 20 t j = 50 c 15 breakdown voltage bv dss t j = 25 c see figure 20 700 v drain supply voltage 50 v auto-restart on-time t ar-on t on i fb = 2 ma- s, f osc = 12 khz v fb = 0 see notes 1, 5 450 ms auto-restart off-time t ar-off 4s open-loop fb pin current threshold i ol see note 5 -120 a open-loop on-time see note 5 90 s notes: auto-restart on-time is a function of switching frequency programmed by t on x i fb and minimum frequency in cc mode. the current limit threshold is compensated to cancel the effect of current limit delay. as a result the output current stays co nstant across the input line range. i dss1 is the worst case off state leakage speci? cation at 80% of bv dss and maximum operating junction temperature. i dss2 is a typical speci? cation under worst case application conditions (recti? ed 265 vac) for no-load consumption calculations. when the duty-cycle exceeds dc max the linkswitch-ii operates in on-time extension mode. this parameter is derived from characterization. 1. 2. 3. 4. 5.
rev. c 06/08 11 lnk603-606/613-616 www.powerint.com 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) current limit (normalized to 25 c) pi-5085-040508 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) frequency (normalized to 25 c) pi-5086-041008 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) frequency ratio (normalized to 25 c) pi-5087-040508 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) frequency ratio (normalized to 25 c) pi-5088-040508 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) feedback voltage (normalized to 25 c) pi-5089-040508 1.200 0.600 0.800 1.000 0.200 0.400 0.000 -40 -15 10 35 60 85 110 135 temperature (c) normalized output current (normalized to 25 c) pi-5090-040508 figure 9. current limit vs, temperature. figure 10. output frequency vs, temperature. figure 11. frequency ratio vs, temperature (constant current). figure 12. frequency ratio vs, temperature (inductor current) . figure 13. feedback voltage vs, temperature. figure 14. normalized output current vs, temperature. typical performance characteristics
rev. c 06/08 12 lnk603-606/613-616 www.powerint.com figure 15. breakdown vs. temperature. typical performance characteristics (cont.) 1.1 1.0 0. 9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) b rea kd own v o l tage (normalized to 25 c) pi-2213-012301 drain volta g e (v) drain c urrent (ma) 300 250 200 100 50 150 0 0 2 4 6 8 10 t case =25 c t case =100 c pi-5082-040408 lnk6x3 1.0 lnk6x4 1.0 lnk6x5 1.5 lnk6x6 2.5 scaling factors: drain voltage (v) drain c apacitance (pf) pi-5083-040408 0 100 200 300 400 500 600 1 10 100 1000 lnk6x3 1.0 lnk6x4 1.0 lnk6x5 1.5 lnk6x6 2.5 scaling factors: 50 30 40 10 20 0 0 200 400 600 drain volta g e (v) power (mw) pi-5084-040408 lnk6x3 1.0 lnk6x4 1.0 lnk6x5 1.5 lnk6x6 2.5 scaling factors: figure 16. output characteristic. figure 17. c oss vs. drain voltage. figure 18. drain capacitance power.
rev. c 06/08 13 lnk603-606/613-616 www.powerint.com figure 19. test set-up for feedback pin measurements. pi-4 9 61-022708 6.2 v 500 1) raise v bp voltage from 0 v to 6.2 v, down to 4.5 v, up to 6.2 v 2) raise v in until cycle skipping occurs at v out to measure v fbth 3) reduce v in until cycle skipping stops at v out to measure v fbth- . cable drop compensaion factor is fb = v fbth / v fbth- 4) apply 1.5 v at v in and measure t fb delay from start of cycle falling edge to the next falling edge s d s s fb s 10 f bp + 2 v + v in + v out linkswitch-ii figure 20. test set-up for leakage and breakdown tests. pi-4 9 62-040308 16 v to measure bv dss , i dss1 , and i dss2 follow these steps: 1) close s1, open s2 2) power-up v in source (16 v) 3) open s1, close s2 4 ) measure i/v characteristics of drain p in usin g the curve tracer s d s s fb s .1 f 1 f bp v in linkswitch-ii 5 f 50 k + curve tracer s1 s2 4 k 10 k
rev. c 06/08 14 lnk603-606/613-616 www.powerint.com figure 21. test set-up for output current measurements. pi-4 9 63-022708 50 v 1)the transformer inductance is chosen to set the value of t on i fb to 2 ma s 2) r o is chosen to operate test circuit in the cc region 3) v o is measured 4) output current is v o / r o s d s s fb s 10 f bp linkswitch-ii 200 200 v 470 pf 680 f 3.3 v r o 11.5 k 7.15 k + v o +
rev. c 06/08 15 lnk603-606/613-616 www.powerint.com notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b 7/85) for standard dual-in-line (dip) package with .300 inch row spacing. 2. controlling dimensions are inches. millimeter sizes are shown in parentheses. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. the notch and/or dimple are aids in locating pin 1. pin 3 is omitted. 5. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 6. lead width measured at package body. 7. lead spacing measured with the leads constrained to be perpendicular to plane t. .008 (.20) .015 (.38) .300 (7.62) bsc (note 7) .300 (7.62) .390 (9.91) .367 (9.32) .387 (9.83) .240 (6.10) .260 (6.60) .125 (3.18) .145 (3.68) .057 (1.45) .068 (1.73) .120 (3.05) .140 (3.56) .015 (.38) minimum .048 (1.22) .053 (1.35) .100 (2.54) bsc .014 (.36) .022 (.56) -e- pin 1 seating plane -d- -t- p08c dip-8c (p package) pi-3 9 33-101507 d s .004 (.10) t e d s .010 (.25) m (note 6) .137 (3.48) minimum smd-8c (g package) pi-4015-101507 .004 (.10) .012 (.30) .036 (0.91) .044 (1.12) .004 (.10) 0 - 8 .367 (9.32) .387 (9.83) .048 (1.22) .009 (.23) .053 (1.35) .032 (.81) .037 (.94) .125 (3.18) .145 (3.68) -d- notes: 1. controlling dimensions are inches. millimeter sizes are shown in parentheses. 2. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 3. pin locations start with pin 1, and continue counter-clock- wise to pin 8 when viewed from the top. pin 3 is omitted. 4. minimum metal to metal spacing at the package body for the omitted lead location is .137 inch (3.48 mm). 5. lead width measured at package body. 6. d and e are referenced datums on the package body. .057 (1.45) .068 (1.73) (note 5) e s .100 (2.54) (bsc) .372 (9.45) .240 (6.10) .388 (9.86) .260 (6.60) .010 (.25) -e- pin 1 d s .004 (.10) g08c .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions .137 (3.48) minimum
rev. c 06/08 16 lnk603-606/613-616 www.powerint.com part ordering information ? linkswitch product family ? ii series number ? package identi? er g plastic surface mount dip p plastic dip d plastic so-8 ? package material g green: halogen free and rohs compliant ? tape & reel and other options blank standard con? gurations tl tape & reel, 1 k pcs minimum for g package. 2.5 k pcs for d package. not available for p package. lnk 615 d g - tl pi-4526-040207 d07c so-8c 3.90 (0.154) bsc notes: 1. jedec reference: ms-012. 2. package outline exclusive of mold flash and metal burr. 3. package outline inclusive of plating thickness. 4. datums a and b to be determined at datum plane h. 5. controlling dimensions are in millimeters. inch dimensions are shown in parenthesis. angles in degrees. 0.20 (0.008) c 2x 1 4 5 8 2 6.00 (0.236) bsc d 4 a 4.90 (0.193) bsc 2 0.10 (0.004) c 2x d 0.10 (0.004) c 2x a-b 1.27 (0.050) bsc 7x 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) m c a-b d 0.25 (0.010) 0.10 (0.004) (0.049 - 0.065) 1.25 - 1.65 1.75 (0.069) 1.35 (0.053) 0.10 (0.004) c 7x c h o 1.27 (0.050) 0.40 (0.016) gauge plane 0 - 8 1.04 (0.041) ref 0.25 (0.010) bsc seating plane 0.25 (0.010) 0.17 (0.007) detail a detail a c seating plane pin 1 id b 4 + + + 4.90 (0.193) 1.27 (0.050) 0.60 (0.024) 2.00 (0.079) reference solder pad dimensions +
rev. c 06/08 17 lnk603-606/613-616 www.powerint.com notes
rev. c 06/08 18 lnk603-606/613-616 www.powerint.com notes
rev. c 06/08 19 lnk603-606/613-616 www.powerint.com notes
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integra tions. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a licens e under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in s igni? cant injury or death to the user. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2008, power integrations, inc. 1. 2. power integrations worldwide sales support locations germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokohama, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date c final data sheet 06/08 world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) room 1601/1610, tower 1 kerry everbright city no. 218 tianmu road west shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com

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